Résumé
In-memory computing (IMC) enables highthroughput, energy-efficient deep neural network inference, but scalable multi-bit weight representation remains constrained by the difficulty of reliably writing multiple device states, often leading to binary weight-slicing implementations. In this work, we investigate lining up multiple magnetic tunnel junction (MTJ) pillars on the same track to realize compact multilevel cell (MLC) storage. Selective programming is enabled by voltage-gated spin-orbit torque (VGSOT) switching, through voltage-controlled magnetic anisotropy (VCMA) effect. We propose to use multi-pillar SOT-MRAM bitcells to encode up to 7 signed levels. We design an AiMC architecture tailored to multi-pillar VGSOT-MRAM with a time-to-digital converter (TDC) sensing scheme. We show that, compared to binary weight-slicing crossbars, the proposed approach achieves 2.8× better energy efficiency with negligible accuracy degradation on MNIST, CIFAR-10, CIFAR-100, and ImageNet.