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Formal Semantics of H-VHDL
Document de travail   Open Access

Formal Semantics of H-VHDL

Vincent Iampietro

Résumé

This document serves as a reference for the definition of the syntax and semantics of a subset of VHDL named H-VHDL. H-VHDL aims at the definition of synthesizable designs with a synchronous behavior (i.e. the execution of the designs is synchronized with a clock signal).

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