Abstract
Advancements in avionic systems technology demand enhanced resilience against environmental hazards such as radiation, which can compromise the reliability of electronic components through different effects. Among these effects, SEUs (Single-Event Upsets) represent a critical concern, as they induce unintended bit flips in memory elements, affecting data integrity and the system's reliability. The Hardened RISC-V System-on-Chip (HARV-SoC) is a soft-core implementation and was designed to ensure fault tolerance in such conditions through Error Correcting Code (ECC) and redundancy mechanisms, such as Triple Modular Redundancy (TMR). This work presents the HARV-SoC, exploring more features that enhance error analysis and improvements than previous implementations. A fault injection campaign was performed at the ChipIr neutron radiation facility to assess the reliability of the circuit. The results of HARV-SoC are present considering resource utilization and detailed analysis of the observed radiation-induced faults. The system demonstrated robustness through the error handling mechanisms mitigating SEUs and enhanced capabilities for reporting errors, which is essential to ensure processor integrity and minimize failures. These findings highlight the suitability of HARV-SoC for safety-critical avionics applications and provide insights for future enhancements in fault-tolerant RISC-V architectures.