Abstract
While emerging non-volatile memories are a promising low power design solution for modernarchitectures, they suffer from high write-latency and energy consumption. This makes them lessfavorable for first-level caches such as L1 cache, compared to usual SRAM memory. We propose acompiler-based approach to attenuate the cost of write operations in an architecture that integratesmagnetic memory such as the Spin Transfer Torque Random Access Memory (STT-RAM) technologyfor L1 cache.In this deliverable, we present an LLVM optimization to reduce the number of silent stores inmemory (stores that have no impact because they write a value already present in memory at thislocation), therefore mitigating the number of write transactions on STT-RAM memory. We showour recent results that confirm the promising impact of this optimization on energy consumption.We also analyze in details the impact of the application characteristics, the compiler, and variousmicroarchitectural features.