Abstract
Read circuit comprising a read amplifier, and corresponding memory device. A read circuit comprises a read amplifier for amplifying and latching a data signal read, via a bit line, in a memory cell (having a variable resistance) of a resistive memory. The read amplifier comprises: two branches with in each two transistors mounted to form a logic inverter; a capacitor connecting the output of the logic inverter of the first branch with the input of the logic inverter of the second branch; two reference resistors and at least five switches. The variable resistor and the two reference resistors are connected to the input electrode of one of the four transistors, allowing a reduction in power consumption and an improvement in the speed and detection margins. A multi-phase operation allows a read with high detection margins and fast detection phases. The capacitor makes it possible to cancel the effects of mismatching on the structure.