Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process

Pascal Nouet; Alain Toulouse

doi:10.1109/66.572075

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Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process

Article de revue

Avec comité de lecture

Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process

Pascal Nouet et Alain Toulouse

IEEE transactions on semiconductor manufacturing, Vol.10(2), pp.233-241

01/05/1997

DOI: https://doi.org/10.1109/66.572075

Résumé

In this paper, we present a global approach for inter- and intralayer capacitance characterization and modeling. Using an accurate on-chip measurement method, we have characterized realistic test patterns, i.e., test patterns consistent with capacitive couplings encountered in a layout. These reference values have allowed us to point out some limitations of current models and to propose new simple analytical models suitable for small dimension capacitive patterns. This paper emphasizes inter- and intralayer modeling.

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Détails

Titre: Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process
Créateurs - sans rôle: Pascal Nouet
Alain Toulouse
Détails de publication: IEEE transactions on semiconductor manufacturing, Vol.10(2), pp.233-241
Nombre de pages: 9
Identifiants: 99139321409311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Langue: English
Type de ressource: Journal article