Abstract
Single-event double transients (SEDTs) in 65-nm bulk CMOS inverter chains designed with different transistor widths are measured under pulsed laser irradiation. A 3-D TCAD simulations coupled with Monte Carlo calculation are performed to explain the experimental results. It is shown that the SEDTs result from the charge sharing between electrically connected inverters. Inverter chains designed with larger transistors are more resistant to SEDTs than those with smaller transistors for normal incidence. However, it is found through simulation that the advantage of inverter chains designed with larger transistors in suppressing SEDTs is compromised for ion incidence along the well direction. In addition to the transistor size optimization technique, an extra hardened design is needed for better mitigation of SEDTs.