Post-Layout Timing Simulation of CMOS Circuits

Denis Deschacht; Michel Robert; Nadine Azemard; Daniel Auvergne

doi:10.1109/43.238609

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Post-Layout Timing Simulation of CMOS Circuits

Journal article

Peer reviewed

Post-Layout Timing Simulation of CMOS Circuits

Denis Deschacht, Michel Robert, Nadine Azemard and Daniel Auvergne

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.12(8), pp.1170-1177

1993

DOI: https://doi.org/10.1109/43.238609

Abstract

As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes only transitions with gates controlled by events. Extraction of conduction paths from a general decomposition of data paths in unidirectional blocks allows general conflictual situations to be solved. Configuration problems detected during the evaluation, such as pulse rejection and strength conflicts, are illustrated, and effective solutions of conflictual configurations are given. It is shown that the implementation of a two-pass algorithm results in a significant improvement of speed. Execution times have been found to be nearly linear with the node numbers. Comparison of simulation times obtained from other timing simulators is given. SPICE compatibilities of PATH-RUNNER allow automatic real characterization of data paths from post-layout extracted net lists, with SPICE-like accuracy for evaluation of delays on real structures.

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Title: Post-Layout Timing Simulation of CMOS Circuits
Creators - without role: Denis Deschacht - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Michel Robert - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Nadine Azemard - Conception et Test de Systèmes MICroélectroniques
Daniel Auvergne - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Publication Details: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.12(8), pp.1170-1177
Identifiers: 9943372109311
Academic Unit: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Language: English
Resource Type: Journal article
Local Fields: lirmm-00239206