Abstract
We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.