Résumé
Radiation-induced faults pose significant challenges for safety-critical systems in space, avionics, and defense. Single-Event Upsets (SEUs) are a key concern, causing bit flips in memory elements and impacting data integrity and system reliability. The Hardened RISC-V System-on-Chip (HARV-SoC) is a soft-core processor designed to ensure fault tolerance in such conditions, employing in-circuit hardening techniques and structured error reporting to improve fault observability. This work presents an experimental characterization of HARV-SoC implemented on SmartFusion2 and PolarFire FPGAs. The systems were evaluated under neutron and proton irradiation, with different architectural configurations explored. Neutron irradiation results showed that the SmartFusion2-based system experienced fewer events but a higher failure rate, while the PolarFire-based system reported more correctable SEUs and greater resilience. Under proton irradiation, SEU cross-sections in BRAMs of the PolarFire system were up to 7× higher than in neutron tests, and execution time varied by over 8× between platforms due to different design implementations.