Résumé
Testing advanced memories is critical for ensuring SoC quality, especially as smaller transistors increase manufacturing defects occurrence, making traditional SRAM functional testing insufficient. To address this issue, a novel structural testing approach based on the Cell-Aware test methodology has been proposed. Structural test patterns are generated by an Automatic Test Pattern Generator (ATPG) using analog CA models, which are derived from exhaustive analog simulations of SRAM primary blocks. However, generating these CA models through analog simulations is both time-consuming and technologydependent. To overcome this limitation, the TrUnDeL methodology was developed to accelerate CA model generation by combining switch-level graph-based analysis with analog simulations. In this work, we further adapt TrUnDeL to generate CA models solely through switchlevel graph-based simulations, completely eliminating the need for analog simulations. The resulting TrUnDeL CA models are then used by the ATPG to create structural test patterns. Through a validation flow, we demonstrate that these patterns, generated without any analog simulations, achieve nearly the same fault coverage as those produced using exhaustive analog simulations in an SRAM case study. Furthermore, the CA model generation time is drastically reduced from one hour to just fifteen seconds for the same case.