Abstract
The trend towards highly integrated electronic devices leads to the growth of the System-in-Package (SiP) and System-on-Chip (SoC) technologies, where data converters play a major role in the interface between the real analogue world and the digital processing. Testing these converters with accuracy and at a low cost represents a big challenge, because the observability and controllability of these blocks is reduced and the test operation requires a lot of time and expensive analogue instruments. The purpose of this paper is to present a new Design-for-Test (DFT) technique called “Analogue Network of Converters”. This technique aims at testing a set of Analogue-to-Digital Converters (ADC) and Digital-to-Analogue Converters (DAC) in a fully digital setup (using a low cost digital tester). The proposed method relies on a novel processing of the harmonic distortion generated by the converters and requires an extremely simple additional circuitry and interconnects.