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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications
Journal article   Open access   Peer reviewed

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen and Patrick Girard
Microelectronics Journal, Vol.111
05/2021

Abstract

triple-node upset latch design self-recoverability low-cost fault-tolerance
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