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Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview
Journal article   Open access   Peer reviewed

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Politano Gianfranco, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, …
Microprocessors and Microsystems: Embedded Hardware Design , Vol.39(8), pp.1204-1214
01/06/2015

Abstract

Fault injection Statistical models Reliability evaluation
Advanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market.
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