Résumé
With the aggressive shrinking of transistor feature sizes, nano-scale CMOS circuits are becoming more vulnerable to multi-node-upsets, e.g., triple-node-upsets (TNUs) as well as quadruple-node-upsets (QNUs), caused by the effects of harsh radiation. This paper first presents a QNU completely tolerant latch based on so-called TPDICE and the soft error interception module (SIM), namely QNUHL. We further propose an advanced latch, namely QNURHL, which mainly employs 24 interlocked Celements, to provide complete QNU recovery. Simulations based on the HSPICE tool demonstrate the complete QNU tolerance as well as the reasonable overhead for the QNUHL latch and also show that the QNURHL latch is recoverable from any possible QNU and can roughly save silicon area by 11% and power dissipation by 16%, compared to the QNU hardened latch (QRHIL) of the same type. Moreover, an algorithm-based method for the verifications of error tolerance and recovery of latches is proposed. The proposed method can simplify the verifications to demonstrate the capability of node-upset tolerance and/or recovery for latches.