Abstract
The properties of graphene obtained by thermal decomposition of hexagonal silicon carbide (SiC) have been the subject of extensive research for several years.The objective of this thesis is to control a part of the environment of graphene, on 4H-SiC (0001), by the growth parameters. More precisely, I was interested in the influence of these parameters on the surface morphology of SiC(0001) and on the buffer layer (BL) to then study the properties of the graphene obtained.Regarding the surface morphology, thanks to the different options available in the Zenith 100 furnace, we were able to study and highlight the impact of several growth parameters on the width, aspect and height of SiC terraces (0001) below graphene. The parameters in question are the temperature ramp, the growth environment, the use of an intermediate isotherm during the annealing as well as the temperature of the latter. These studies have allowed us to identify a reproducible process, with more than sixty growths, which allows the production of a continuous film of predominantly monolayer graphene that covers the entire surface area ranging from 6 × 6 mm2 up to 10 × 10mm². This film is obtained on straight and wide SiC (0001) terraces, which can reach 12 µm on average, with a height of less than 2.5 nm. To our knowledge, these are the widest 4H-SiC (0001) terraces ever reported under mainly monolayer graphene obtained at an intermediate pressure (50 mbar). The Raman characteristics as well as the electrical properties of this new type of epitaxial graphene sample on 4H-SiC (0001), are presented and discussed. Regarding the electrical properties, after annealing at 575 K, the analyzed sample is n-type with a Hall carrier concentration of 1013 cm-2 and a Hall mobility around 880 cm²V-1s-1. We emphasize that these values are comparable with those already reported for graphene samples epitaxially grown on SiC (0001). Moreover, the new configuration of the terraces that we propose here opens the way to a more in-depth study of the microscopic electrical properties of graphene epitaxially grown on SiC(0001). Indeed, with a width of 12 µm on average, it is now possible to produce Hall bar-type devices on a single terrace and thus access the intrinsic properties of epitaxial graphene, without being disturbed by the edge of the terraces.Regarding the buffer layer, a two-step study was conducted. The first step made it possible to identify a reproducible process allowing the coverage of our samples by this layer. The second step made it possible to identify a rapid process, in less than 35 minutes, allowing this buffer layer to be completely transformed into a graphene layer by intercalation of H2. The mechanisms involved during this intercalation are also discussed. Although this method is relatively recent, it is important to highlight that different groups have already used it (successfully) to obtain monolayers of graphene (1LG) directly on SiC(0001) (1LG/SiC(0001)). Generally, the intercalation is done under a purely H2 environment. In our case, the intercalation is successfully performed under a mixed environment (H2/Ar; 20/80%) which is better from a security perspective. Regarding the properties of the samples produced, the Raman characterizations revealed a low intensity D band on our samples (1LG/SiC(0001)) indicating a low rate of defects. Regarding the electrical properties, one of the samples, 1LG/SiC(0001)), was the subject of extensive measurements and analyses. The measurements carried out revealed that this sample was p-type with a Hall mobility, at 300 K, around 1410 cm²V-1s-1 (comparable to that of silicon). More interestingly, after annealing at 575 K, the evolution of resistivity as a function of temperature could be described by a model (VRH+TA) suggesting the opening of a gap.