Abstract
This thesis focuses on the reduction of testing costs for RF integrated circuits. The original approach that is investigated relies on the use of a standard digital ATE to perform an under-sampled acquisition of the RF signal to be analyzed. The basic idea is to use the comparator present in a digital tester channel to convert the RF signal into a binary sequence. During this conversion, the information carried by the RF signal (amplitude, frequency, phase ...) is transformed into a timing information contained in the binary vector captured by the ATE. The objective is then to develop dedicated processing algorithms able to retrieve the essential RF signal characteristics from the analysis of the binary vector. The major benefit of this solution is that it eliminates the need of expensive RF test resources traditionally required. In addition, since digital channels are generally available in large numbers on a standard ATE, this approach also provides the ability to implement multi-site tests to further reduce testing costs. In this thesis, the proposed approach is implemented for ZigBee Transceiver from NXP Semiconductors operating at 2.4 GHz and intended for the growing market of Internet of Things (IoT). The under-sampling conditions allowing to preserve the information contained in the RF signal while respecting the test equipment constraints are defined and dedicated algorithms are developed to implement the various tests specified by IEEE Std 802.15.4 ™ (power test, spectral mask test, EVM measurements). The proposed solution is first evaluated in simulation within the Matlab environment. A laboratory test bench is then developed to carry out an initial validation. Finally, measurements performed with an ATE on several hundreds of circuits in an industrial environment fully validate the proposed solution.