Abstract
The first part of this thesis recalls the involvement of electrostatic discharge within submicron CMOS circuits, ways of assessing the protection of a circuit and the different protection strategies commonly used to protect a circuit against ESD events and also presents the results obtained silicon structures test using the parasitic bipolar as a protective element (ggNMOS, LVTpnp). Since then, our work has focused on design and development of protections central using MOS conduction in order to evacuate ESD current. We bring a significant improvement in particular with untimely triggers caused by the phenomena of noise encountered on power supplies. A robust design of the circuit and a trigger approach to overcome the adverse effects encountered with very slow supply ramp-up is also presented. Thereafter we propose a method for the design of a central dynamic protection associated with the submission of a comprehensive flood automated characterization in the context of the use of a comprehensive strategy for the protection of a circuit. The last part of this work proposes two new approaches regarding detection function which could make very fast power up without causing the outbreak of protection that can lead to a static critical current consumption.