Abstract
The reliability of electronic circuits is subject to physical damage or functional failures due to the influence of the application environment, such as the presence of atmospheric or space radiation. The particle interaction within silicon can lead to permanent or transient effects such as the Single-Event Effects (SEEs). Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET must be carefully addressed along with the SEU characterization in electronics systems from space to ground applications. Also, to increase the reliability of the systems, radiation hardening techniques can be adopted in the process or design levels. The characterization process is usually experimental-test oriented, however, the need of adopting modeling simulations to study fundamental radiation effects and improve testing methodologies has led to an increase interest in developing SEE characterization methodologies based on simulation tools. Accordingly, this thesis provides a complete simulation chain based on a multi-physics and multi-scale approach to characterize electronics component against SEU/SET effects. Additionally, radiation-hardening-by-design (RHBD) techniques were evaluated and proposed at physical layout and circuit levels. The physical layout design influences the SEE generation mechanisms induced by a particle strike hence hardening techniques are widely used in the layout level to reduce the charge collection process. Besides analyzing the gate sizing and transistor stacking, in this work, the transistor folding layout is proposed along with the diffusion splitting technique. The results have shown that folded designs can provide lower SET cross-section in addition to the higher threshold LET than the observed for the unfolded designs. At circuit-level, the implications of logic synthesis of cell-based designs are studied. Additionally, given the input dependence of the RHBD techniques, signal probability is proposed as an application-specific hardening approach in order to improve the hardening efficiency while reducing the design drawbacks and, very importantly, avoid misleading qualifications. For instance, a pin assignment optimization targeting SET effects can provide reduction on the overall SET rate without any area overhead. Additionally, selective TMR (Triple Modular Redundancy) block insertion methodologies can be optimized based on the signal probability of the critical nodes and the majority voter architectures.