Abstract
Today's embedded systems are considered as non trusted hosts since the owner, or anyone else who<br />succeeds in getting access, is a potential adversary. The bus between the System on Chip (SoC) and the external<br />memory is one of the weakest points of such systems because external memories contain sensitive data (end<br />users private data, software code...) which are usually exchanged in clear form over the bus. Therefore an<br />adversary may probe this bus in order to read private data or to retrieve software code (data confidentiality<br />concern). Another possible attack relies on code injection (data integrity concern). Thus, hardware mechanisms<br />must be designed to ensure data confidentiality and integrity. The conventional way to reach such a goal is to<br />implement a dedicated hardware engine for each security service. Being secured, this approach prevents<br />parallelizability of the underlying computations.<br />In this thesis, after a study of existing techniques and engines guaranteeing data confidentiality and<br />integrity, two hardware mechanisms dedicated to the security of processor-memory transactions are proposed.<br />First, a Parallelized Encryption and Integrity Checking Engine (PE-ICE) has been designed to provide an<br />effective solution to ensure both security services to data. PE-ICE allows full parallelizations on processor read<br />and write operations while optimizing the hardware resources required. Then, a technique based on a tree<br />structure (PRV-Tree – PE-ICE protected Reference Values) with the same property of full parallelization, is<br />specified to decrease the on-chip memory overhead implied by security mechanisms.