Résumé
This thesis deals with the characterization and analytical or semi-analytical modeling of the effects related to miniaturization of MOS transistor in order to develop physical models for device characterization. In a first part, various key points of the optimization of nanometric MOSFETs are reviewed, pointing out the limits of CMOS technologies. Then, our study focuses on the effects of quantum confinement and on high gate currents in MOS structures with ultrathin dielectrics. We propose a model of surface potential taking into account of the quantum and polydepletion effects in all regions of operation. A long channel MOS transistor model based on the charge sheet approximation and using the quantum surface potential model has been developed for the extraction of the technological and conduction parameters of 65 nm technology node transistors under high gate leakage conditions. Moreover, a small signal non quasi static model has been developed for the characterization of large area MOS structures. The last part of this thesis is devoted to modeling the low frequency noise related to ultrathin gate dielectrics, in particular to low frequency noise associated to the gate current. These models are used for the characterization of the ultrathin dielectric film by low frequency gate current noise measurements.