Abstract
More computing cores are now being integrated on a single chip in order to meet the ever-growing application demands for high performance and low power computing systems. As the number of cores continues to grow, so is the demand for scalable on-chip communication networks that can deliver high-speed communication among the cores. Contrary to traditional on-chip networks, Networks-on-Chip (NoCs) have emerged as a mature alternative interconnect for manycore architectures since it provides enhanced scalability and power efficiency.Typical NoC routers consist of buffers which serve as temporary data storage. However, studies have shown that buffers are often unutilized (i.e. idle or underutilized) especially when executing applications with non-uniform traffic patterns or bursty behaviours. This is because most typical routers dedicate a set of buffers to their input and/or output ports and these buffers can only be exploited by data-flows using them, which leads to significant performance degradation. Therefore, router architectures capable of maximizing buffer utilization for performance gains are indispensable.In order to maximize buffer resource utilization, this thesis proposes a novel NoC router concept called Roundabout NoC (RiNoC) that is inspired by real-life multi-lanes traffic roundabout. Contrary to existing approaches, RiNoC provides intrinsic and effective resource utilization. However, roundabout-inspired routers are susceptible to deadlocks due to their ring-like architecture. The Rotary NoC router shares similar ring-like concept with propose but relies on a deadlock-free technique which introduces significant area/power overheads. Conversely, RiNoC achieves deadlock-freeness and enhanced network performance over typical NoCs without compromising network area/power. This thesis further exploits RiNoC highly parametric architecture in order to produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.