Abstract
Improving only the performance and energy efficiency of transistors is not sufficient for future systems-on-chip. On-chip interconnects have become equally critical to transistors and can detriment the system’s performance and energy efficiency. Copper (Cu) is the state-of-the-art interconnect material and is reaching its physical limitations due to scaling. Barrier and scattering effects induce high resistivity and electromigration exacerbates interconnect reliability. Carbon Nanotubes (CNTs) and Copper-Carbon Nanotube (Cu-CNT) composite materials are of interest due to ballistic transport, high scalability, high thermal conductivity, and high current density. We investigate from fundamental atomistic level to macroscopic level the physical understanding and electrical compact modeling on CNT and Cu-CNT composite for on-chip local and global interconnect applications. We evaluate and assess the different sources of variations and their impacts on CNT interconnect performance and energy efficiency. Charge transfer based doping of CNT is also investigated as an alternative method to further reduce its resistivity, mitigate CNT chirality variations and contact resistance drawbacks. Experimental measurement results are used to demonstrate the validity and accuracy of our established models. The interconnect models are finally applied to the gate- and circuit- level studies as local and global interconnects to evaluate their performance.