Abstract
The work presented in this manuscript involves analysis, design methods and search for improved structures of current sources, with main focus on the current mirrors, the most elementary current source. The main objective of our research was to outperform the present limitations in terms of speed, power and accuracy that exists in CMOS current mirror design.In the first part of the manuscript, we investigate on the origin of these limitations and present a literature review of popular and recent advanced current mirror structures. Then follow a deeper analysis of active-input current mirror capabilities. The first scientific contributions were, the development of analytical tools dedicated to the implementation of the standard active-input topology, supported by two solutions for dynamic range and stability improvements at minimal costs.The proposition of a novel design approach, relying on a power-efficient speed boosting technique based on current-mode non-linear control loops, constitutes the major contribution of the work presented in this manuscript. The feedback circuit is implemented using a custom low-power current conveyor (CCII), built to be intentionally non-linear. Coupled with classical regulated cascode structures required for high-precision current copy, this enhanced active-input current mirror topology forms a new competitive elementary current source to the design of high-performance systems.The approach is validated and illustrated with the realization of two circuits in 180 nm CMOS technology. Cores of the circuits are two examples of output stages dedicated to neural stimulation chips. Finally, Results of the last studies have demonstrated that, thanks to the design strategy and the new active-input current mirror topologies proposed, it is actually possible to outperform the present limit of the speed-power-accuracy trade-off.