Abstract
This thesis explores the development and characterization of the HARV processor and its HARV-SoC version, specifically designed for operation in harsh environments. It begins by highlighting the challenges posed by harsh environments, particularly the impact of radiation on electronic devices and systems. The thesis categorizes harsh environments into space, atmospheric, and artificial radiation environments, each with its unique characteristics.In the artificial radiation environments, various experimental facilities are described, which provide different particle spectra, including neutrons, protons, and mixed fields. The thesis delves into the radiation effects on electronic devices, covering cumulative effects like total ionizing dose (TID) and displacement damage (DD), as well as single events leading to errors and system failures.The research introduces the RISC-V Instruction Set Architecture (ISA) as a widely adopted processor architecture known for its regular instruction formatting, cost-effective instruction decoding, and modular flexibility. The thesis emphasizes the importance of reliability in using processors in harsh environments and discusses techniques for error detection and correction, including spatial, temporal, and information redundancy.Acknowledging the increasing use of RISC-V processors in critical applications, the thesis summarizes related work, positioning HARV-SoC in the context of the latest developments. It then delves into the implementation of HARV, the initial version of the processor, emphasizing microarchitecture-level fault tolerance. Register protection using error-correcting codes and triple modular redundancy is highlighted.The work extends to developing an SoC with a multi-cycle architecture, allowing for more complex applications while maintaining essential peripherals. Fault injection simulations are conducted to analyze fault models comprehensively. Observability mechanisms are introduced to prepare HARV-SoC for experiments in particle accelerators, enabling a detailed analysis of errors within the processor, particularly with neutron radiation.Recognizing the limitations of error counters, an error handler is implemented to temporarily store information about detected errors. This information is reported to applications through exceptions, facilitating detailed error analysis and responses. The design is thoroughly characterized and evaluated in experiments involving various radiation environments.The analysis expands to testing operating systems and using software recovery techniques. In conclusion, the thesis comprehensively explores radiation-tolerant processors for harsh environments, providing valuable insights and techniques to enhance system reliability and performance in challenging scenarios.