Abstract
Transistor downscaling allows processors to continuously increase transistor density and to operate at higher frequencies. Although downscaling leads to higher performance and lower power consumption, each new CMOS technology node is facing reliability issues due to increasing rate of faults and errors that occur in electronic devices despite careful design and manufacturing processes. Consequently, most of systems today include fault-tolerant techniques that ensure correct operations of digital parts. These techniques employ redundancy to ensure that faults cannot cause system failures. This thesis studies the cost/reliability trade-off on fault-tolerant architectures based on structural redundancy exploiting the low-cost advantages of the approximate computing paradigm. The first contribution of the thesis is a selective hardening scheme that achieves fault detection with a duplication scheme that compares a precise and approximate version of the circuit. The second contribution of the thesis is a fault-tolerant architecture, called QAMR, which is able to mask the same faults that a TMR would, but at lower cost. Results of these works show that an appropriate use of approximate computing in redundancy schemes can achieve, at lower cost, the same reliability level than traditional techniques.