Abstract
Flash memories are non-volatile memories present in a growing number of integrated circuits used in portable electronic devices. The non-volatility, low power consumption and flexibility make them extremely popular. Nevertheless, the reliability is a characteristic to improve as far as area needs increase and critical applications are targeted. Effectives fault tolerance solutions that are low cost and that can be easily integrated must be found. In a first time, the work of this thesis was focused on the analysis and the study of Flash reliability. It was the occasion to establish a reliability model for a floating gate cell depending on various parameters. This model was adjusted depending<br />on parameters coming from a 180 nm technology. In a second time, the work was dedicated on the development of two fault tolerance techniques merging error correcting codes and redundancy. The first technique, called error correction by VT analysis, provides an extended correction capacity by analyzing the charge level of cells. A mathematical study and next, a reliability architecture have been proposed. In this study, it is supposed that a given number of redundancy resources are available to repair the memory as soon as an error is detected. The second developed technique, called hierarchical error correction, uses the fact that correction capacities can be distributed in an original<br />way into the memory to significantly reduce the cost usually associated with advanced error correction techniques. This code has also been integrated in a reliability architecture having some redundancy resources. A mathematical study based on Continuous Time Markov Chain has allowed to demonstrate the effectiveness of this structure. Developed techniques are alternatives solutions to standard scheme used in the industry. They allows to improve significantly the mean time to failure of a system by many times at a reasonable area cost.