Abstract
Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are new innovations in silicon process technologies that are likely alternatives to traditional planar Bulk transistors due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit.The work of this thesis is focused on implementing similar design in each technology and comparing the electrical behavior of the circuit with the same defect. The defects that are considered for our investigation are inter-gate resistive bridging, resistive short to ground terminal (GND), resistive short to power supply (VDD) and resistive open defects. Defect detectability is evaluated in the context of either logic or delay based test. HSPICE and Cadence SPECTRE simulations are performed varying the value of the defect resistance and the concept of critical resistance is used to compare the defect detectability range in different technologies. The optimal body-biasing, supply voltage and temperature settings to achieve the maximum defect coverage are determined for these defect types. An analytical analysis is proposed for short defects based on the ON-resistance of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. Testability properties are also established under the presence of process variations based on Monte-Carlo simulations for both Regular-VT devices (FDSOI-RVT and Bulk-LR) and Low-VT devices (FDSOI-LVT and Bulk-LL) available for 28nm Bulk and FDSOI technologies.