Abstract
Computer system architectures have become increasingly complex. Pushing for better performance and lower energy consumption, they include multiple cores, GPUs, accelerators, and sophisticated memory hierarchies. In this context, computer system simulators play a significant role in the research architecture community. They allow the evaluation of new architecture ideas while being quicker and avoiding the huge costs of manufacturing processes.The simulated architectures are often compared with real state-of-the-art baseline architectures. Thus, the relevance of the conclusions from such simulators is directly related to the faithfulness of the baseline model. We observe that having strong baselines is not a simple task due to the lack of detailed technical information about commercial architectures. In this thesis, we propose a systematic methodology to extract information from real commercial architectures for the calibration of their corresponding simulation models. This methodology is based on handcrafted microbenchmarks that leverage hardware performance counters for non-intrusive monitoring. We instantiate this methodology on two key components of the architecture.First, we target the different levels of the memory hierarchy. We design the microbenchmarks to produce a signature of the memory system levels. The signature contains parameter values that are important to calibrate a simulation model of the real architecture. We implement the methodology with the gem5 simulator and an ARM Cortex-A53 CPU. Then, we evaluate our methodology with benchmarks from the SPEC CPU2006 suite. The benchmarks are executed on the commercial CPU and gem5 using our calibrated configuration. The results show that our calibration reduces the average and maximum simulation error by 43% and 62%, respectively.Second, we instantiate the methodology on the data prefetching engine, which is a key component of the memory system that can generate memory requests in parallel to the core. This new instantiation of our methodology results in Pref-X, a framework that enables functional analysis of data prefetching engines in in-order cores. For that, the framework uses memory request sequences to stress the L1 data cache and expose the changes in L1 cache content. From those changes, Pref-X deduces the functional specifications of the data prefetching engine. Finally, we use the extracted information to build a functional model of the prefetching engine. We apply Pref-X to two in-order ARM CPUs, the Cortex-A7 and the Cortex-A53, and evaluate its accuracy with memory traces extracted from the SPEC CPU2006 suite. We execute the traces on both the commercial CPUs and their corresponding functional models produced by our framework. The results show an average prefetching accuracy of 99.8% and 96.9% for the Cortex-A7 and the Cortex-A53, respectively.This thesis builds a detailed understanding of how microbenchmarks can be used to improve the modeling accuracy of existing architectures. We believe our methodology has the potential to be applied to other components beyond the ones covered in this manuscript, but that is part of future work. We hope our results will enable the community to use better-calibrated baseline architectures in their simulations.