Résumé
The manufacturing of modern Integrated Circuits (IC), resistant to faults caused by ionising radiation, has become quite challenging due to the rapid advancement of VLSI technology. Existing literature employs a combination of simulation-based and analytical methods to achieve efficient Single Event Transients (SET) analysis. In this work, we propose a novel Electronic Design Automation (EDA) analysis approach for SETs, called UPSET. UPSET can handle VLSI circuits with thousands of gates since it relies on the industry-proven Static Timing Analysis (STA) methodology. Notably, it performs a complete SET analysis, without the need of extra characterisation, while providing an understanding of the circuit sensitivity to SETs. Experimental analysis demonstrates that our methodology achieves a significant ×25,222 speedup, while providing a tight upper bound with 4.56% relative error, against SPICE simulation.