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Timing-aware ATPG for critical paths with multiple TSVs
Acte de colloque

Timing-aware ATPG for critical paths with multiple TSVs

Carolina Momo Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard et Arnaud Virazel
17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.116-121
DDECS: Design and Diagnostics of Electronic Circuits and Systems (Warsaw, Poland, 23/04/2014–25/04/2014)
2014

Résumé

Defective TSVs Commercial ATPG tools Multiple TSVs Path delay variations Small delay faults Small delay variations Statistical delay quality level Test patterns Through-silicon-vias Timing-aware ATPG Automatic test pattern generation Circuit faults SDF detectability IR-drop 3D-IC reliability SDQL metric TSV testing quality Integrated circuit reliability Electrical conditions Integrated circuit testing Three-dimensional integrated circuits Small-delay faults Delays Three-dimensional displays 3D integration technology 3D integration Through-Silicon vias Resistive open defects Critical paths

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