Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture

Yannick Bonhomme; Tomokazu Yoneda; Hideo Fujiwara; Patrick Girard

Retour

Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture

Acte de colloque

Open Access

Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture

Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara et Patrick Girard

8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.19-26

8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (Sopron, Hungary, 13/04/2005–16/04/2005)

2005

Résumé

DFT

Scan Testing

Scan Tree

A dynamically reconfigurable scan tree architecture is proposed to reduce (up to 95%) test application time and test data volume of standard scan architectures. Additional important aspects, such as the impact of the new architecture on circuit performance and DFT area, are also considered in this paper.

Fichiers et liens (1)

url

Find in HALAfficher

Indicateurs

1 Consultations de la notice

Détails

Titre: Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture
Créateurs - sans rôle: Yannick Bonhomme - Nara Institute of Science and Technology
Tomokazu Yoneda - Nara Institute of Science and Technology
Hideo Fujiwara - Nara Institute of Science and Technology
Patrick Girard - Conception et Test de Systèmes MICroélectroniques
Détails de publication: 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.19-26
Colloque: 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (Sopron, Hungary, 13/04/2005–16/04/2005)
Identifiants: 9946861009311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00105987