Logo image
Se connecter
Retour
Switch level test pattern production for CMOS ICs
Acte de colloque

Switch level test pattern production for CMOS ICs

M.-L. Flottes, C. Landrault et S. Pravossoudovitch
Proceedings : advanced computer technology, reliable systems, and applications : 5th Annual European Computer Conference, Bologna, May 13-16, 1991, pp.672-679
1991
DOI: https://doi.org/10.1109/CMPEUR.1991.257470

Résumé

Automatic control Circuit faults Circuit testing Macrocell networks Production Programmable logic arrays Semiconductor device modeling Sequential analysis Switches Very large scale integration
An overview is presented of the different possibilities which allow the implementation of switch-level test pattern production for CMOS macrocells. A discussion is presented of fault modeling, fault list generation, circuit modeling and fault equivalence. Switch-level fault simulation is outlined along with switch-level ATPG (automatic test pattern generation).< >

Indicateurs

1 Consultations de la notice

Détails

Logo image