Résumé
Silicon photonic integrated circuits (PICs) have become indispensable in modern technology, and are particularly valuable in applications such as high-speed telecommunications, data centers, artificial intelligence or sensing. The monolithic integration of III-V lasers on Silicon (Si) substrates has attracted considerable attention to combine the optoelectronic properties of light sources with the well-established Si industry technology. However, epitaxially integrated III-V devices on Si suffer from a severe lack of reliability because of the large crystal defect density. For instance, polar on non-polar heteroepitaxy, or lattice mismatch are responsible for forming antiphase boundaries (APBs) and dislocations. The high density of threading dislocations (TDs) ~ 7x1E8 cm-2 in our layers degrades the laser's performances and reduces their lifetime. Therefore, a reduction of the threading dislocations density (TDD) is a prerequisite for the reliability of integrated devices. Many techniques for TDD reduction have been reported in the literature such as thermal cycling annealing (TCAs), or dislocation filtering layers (DFLs). Using Electron Channeling Contrast Imaging (ECCI) and Transmission Electron Microscopy (TEM), we conducted an extensive study of the dislocation networks at the interfaces of an AlSb DFL inserted in a GaSb buffer layer. Our presentation will address the effect of TCAs, DFL thickness and cap thickness on the TDD. It was found that the sole insertion of a 300 nm interfacial AlSb layer helps reduce the TDD by one order of magnitude. While the understanding of interfacial misfit network formation is limited in the literature, we will propose a strain relaxation mechanism for the DFL interfaces. These initial findings are promising, and motivate new exploration paths like coupling several AlSb layers, to further reduce the TDD for optimizing the performance, and reliability of optoelectronic devices.