Résumé
The RISC-V Vector Extension (RVVE) enhances computational efficiency by exploring data-level parallelism, which can benefit Artificial Intelligence (AI) applications. The Zve32x subset is tailored for embedded systems, including those in space, in which AI applications are very useful to process data onboard. However, environments like space challenge the reliable functioning of electronic systems due to radiation exposure and extreme temperatures. Thus, fault tolerance techniques are crucial to mitigate potential failures. Therefore, we extended a previous implementation of a subset of the RVVE to the HARV-SoC, a fault-tolerant RISC-V-based system-on-chip, to add support to multiplication operations, which are essential in AI applications. We also added support to more configuration instructions that allow increasing the number of elements that are processed with a single instruction, further accelerating the processing. We evaluated the impact of the vector instructions over the scalar ones using C and Assembly applications to evaluate the impact of vector intrinsic functions. We estimated the reliability of the core through simulations based on fault injection campaigns with both baseline and hardened HARV-SoC. The results show that the vector unit of Fers a performance acceleration of up to 28.69 times with manual code optimization and can enhance reliability. Furthermore, this work assesses how different configurations of the vector parameters affect the performance and reliability.