Résumé
As digital systems become increasingly integrated into radiation-prone environments, such as aerospace, automotive, and edge computing platforms, their ability to operate reliably under radiation-induced faults is essential. These faults, ranging from transient disruptions to permanent errors, can affect various system layers. In this work, we present an investigation into such challenges, combining simulation-based fault analysis with experimental validation. We introduce a novel methodology for modeling Single Event Transients (SETs) in clock distribution networks, enabling precise evaluation of Flip-Flop (FF) sensitivity. Additionally, a cross-layer framework is introduced to analyze how low-level hardware faults affect inference behavior in Dynamic Neural Networks (DyNNs), highlighting the unique reliability challenges posed by adaptive neural architectures. Finally, we present neutron irradiation results from a soft-core fault-tolerant RISC-V SoC implemented on an SRAM-based FPGA, revealing the critical role of architectural mitigation strategies for Single-Event Upsets (SEUs) and preserving system functionality.