Security Evaluation of Dual Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe; Philippe Maurine; Michel Robert; Marc Renaudin

doi:10.1109/VLSISOC.2006.313230

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Security Evaluation of Dual Rail Logic Against DPA Attacks

Acte de colloque

Open Access

Security Evaluation of Dual Rail Logic Against DPA Attacks

Hanitriniaina Razafindraibe, Philippe Maurine, Michel Robert et Marc Renaudin

VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, pp.181-186

VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration (Nice, France, 16/10/2006–18/10/2006)

2006

DOI: https://doi.org/10.1109/VLSISOC.2006.313230

Résumé

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust.

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Titre: Security Evaluation of Dual Rail Logic Against DPA Attacks
Créateurs - sans rôle: Hanitriniaina Razafindraibe - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Philippe Maurine - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Michel Robert - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Marc Renaudin - Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Détails de publication: VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, pp.181-186
Colloque: VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration (Nice, France, 16/10/2006–18/10/2006)
Identifiants: 9946946909311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00109692