Résumé
The past two decades have seen the increasing attractiveness of programmable circuits that proved its validation role in the logic design flow and its high level of flexibility. At the same time, asynchronous circuits are more and more used in order to remove the clock distribution problems and the power consumption overhead which drastically increases with frequency. Several programmable asynchronous circuits have been proposed. Most of them are dedicated either to a specific asynchronous circuit style (PGA-STC[4], PAPA[6]) or to a dedicated application (MONTAGE[3], GALSA [5]). In this paper, we present a novel architecture which is more flexible than the actual asynchronous programmable circuits and which is natively robust to Side Channel attacks and Fault attacks (SCAs and FAs). Indeed, the proposed architecture supports special features such as 1-of-n encoding, and different handshake communication protocols (2-phase and 4-phase).