Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Nadine Azemard; Michel Aline; Daniel Auvergne

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Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Nadine Azemard, Michel Aline et Daniel Auvergne

9th International Workshop on Power and Timing Modeling Optimization and Simulation, pp.325-334

PATMOS: Power And Timing Modeling, Optimization and Simulation (Kos, Greece, 05/10/1999–08/10/1999)

1999

Résumé

This paper adresses the problem of satisfying delay/power constraints using a post layout iterative gate sizing. Path sizing procedure is defined with a realistic evaluation of gate delay and power and an accurate estimation of parasitic capacitances. This sizing protocol is validated on ISCAS'85 benchmarks, and implemented in a prototype for Performance Optimization by Path selection (POPS). The efficiency of this sizing heuristic is compared to an industrial optimization tool, AMPS (Synopsis).

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Détails

Titre: Satisfaction of Delay/Power Constraints by Iterative Gate Sizing
Créateurs - sans rôle: Nadine Azemard - Conception et Test de Systèmes MICroélectroniques
Michel Aline - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Daniel Auvergne - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Détails de publication: 9th International Workshop on Power and Timing Modeling Optimization and Simulation, pp.325-334
Colloque: PATMOS: Power And Timing Modeling, Optimization and Simulation (Kos, Greece, 05/10/1999–08/10/1999)
Identifiants: 9943713409311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00244003