Résumé
The reliability of on-chip communication is a key enabler for dependable Multiprocessor System-on-Chip (MPSoC) platforms operating in radiation-harsh environments. This work investigates the fault-tolerance of the eXtensible Interconnect Network Architecture (XINA), a configurable Network-on-Chip (NoC) integrated with an AMBA AXI-compatible Network Interface (NI), both of which employ Triple Modular Redundancy (TMR) in the control logic and Hamming Error-Correcting Codes (ECC) in the data buffers. The evaluation focuses on the interconnection fabric of a 10x10 MPSoC prototype composed of 100 routers and 100 AXI-connected cores, where manager and subordinate IPs act as traffic generators and monitors data integrity under full load. A large-scale fault-injection campaign comprising 1,000 simulations with Single-Event Upset (SEU) injections was conducted to assess the impact of fault-tolerant mechanisms across four hardening configurations. The results demonstrate improved reliability, with the fully protected architecture achieving an 87.2% reduction in observed errors relative to the baseline while maintaining stable throughput and data integrity across all tests. These findings confirm the effectiveness of combining NoC and NI hardening for resilient interconnect design, reinforcing XINA as a dependable and scalable solution for high-reliability MPSoCs in mission-critical applications.