Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell

Retour

Acte de colloque

Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard, Olivier Héron, Serge Pravossoudovitch et Michel Renovell

8th IEEE European Test Workshop, pp.147-152

ETW: European Test Workshop (Maastricht, Netherlands, 25/05/2003–28/05/2003)

2003

Résumé

Fault detection

Table lookup

Programmable logic arrays

Manufacturing

Logic arrays

Integrated circuit interconnections

Field programmable gate arrays

application-oriented test procedure

integrated circuit testing

logic testing

AOTP

LUT dynamic behavior

LUT static behaviour

MOTP

SRAM-based FPGA

Delay

delay fault detection

delay testing

look-up tables

manufacturing oriented test procedure

physical defect detection

test sequence optimization

test vectors

Circuit faults

Circuit testing

The objective of this paper is to analyze the detection of defects located in look-up-tables (LUTs) of SRAM-based FPGAs in the context of delay testing. Firstly, the static and dynamic behaviors of FPGA LUTs are described. Secondly, it is demonstrated that physical defects in FPGA LUTs can create delay faults. The detection of such delay faults is analyzed and requirements on test vectors are derived. Finally, an optimal test sequence, detecting all possible delay faults in a LUT, is defined in the context a manufacturing oriented test procedure (MOTP) as well as in the context of an application-oriented test procedure (AOTP).

Fichiers et liens (1)

url

Find in HALAfficher

Indicateurs

1 Consultations de la notice

Détails

Titre: Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs
Créateurs - sans rôle: Patrick Girard - Conception et Test de Systèmes MICroélectroniques
Olivier Héron - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Serge Pravossoudovitch - Conception et Test de Systèmes MICroélectroniques
Michel Renovell - Conception et Test de Systèmes MICroélectroniques
Détails de publication: 8th IEEE European Test Workshop, pp.147-152
Colloque: ETW: European Test Workshop (Maastricht, Netherlands, 25/05/2003–28/05/2003)
Identifiants: 99152981609311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00269530