Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory

Dorian Ronga; Xhesila Xhafa; Thibault Vayssade; Arnaud Virazel

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Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory

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Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory

Dorian Ronga, Xhesila Xhafa, Thibault Vayssade et Arnaud Virazel

18e Colloque National du GDR SoC² (Toulouse, France, 10/06/2024–12/06/2024)

Résumé

Memory testing

Automatic Test Pattern Generation (ATPG)

Memory model

SRAM

This paper proposes a methodology to produce a digital Verilog-HDL netlist of an SRAM memory, based on an initial SPICE model. The digital model considers the bidirectional nature of the memory, and is ATPG-compliant, allowing the generation of test patterns, and fault simulation.

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Titre: Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM Memory
Créateurs - sans rôle: Dorian Ronga - Test and dEpendability of microelectronic integrated SysTems
Xhesila Xhafa - Test and dEpendability of microelectronic integrated SysTems
Thibault Vayssade - Test and dEpendability of microelectronic integrated SysTems
Arnaud Virazel - Test and dEpendability of microelectronic integrated SysTems
Colloque: 18e Colloque National du GDR SoC² (Toulouse, France, 10/06/2024–12/06/2024)
Identifiants: 9942059309311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-04739569