Résumé
This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IRdrop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IRdrop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).