Résumé
In this paper, we present the Asynchronous In-Place Optimisation (AIPO) algorithm, designed to enhance post-placement-and-routing (post-P&R) timing for asynchronous control and Bundled-Data circuits. AIPO operates in a closed-loop system with ASTA (Asynchronous Static Timing Analysis), focusing on achieving timing closure for the circuit. The algorithm performs gate resizing and buffer insertion by making tentative optimisation moves and evaluating their impact using ASTA. It leverages advanced timing models, such as CCS, and well-established wire RC representation formats, such as Pi-models. Additionally, AIPO works in tandem with a placement legaliser to resolve cell overlaps introduced by its optimisation actions. We present post-P&R results for the AIPO algorithm across 17 benchmark designs and three technology libraries: IHP 250nm, IHP 130nm, and GF 22nm. The results demonstrate that AIPO effectively improves circuit timing by mitigating the adverse effects of cell placement and wire RC interconnect delays. Timing improvements of 33% and 30% were observed for the IHP and GF libraries, respectively. The observed area overhead correlates with the achieved delay reductions, highlighting AIPO's ability to navigate the Area-Delay Pareto trade-off effectively.