Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology

Christophe Entringer; Philippe Flatresse; Pascal Salomé; Pascal Nouet; Florence Azaïs

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Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology

Christophe Entringer, Philippe Flatresse, Pascal Salomé, Pascal Nouet et Florence Azaïs

Electrical Overstress/Electrostatic Discharge Symposium

EOS/ESD: Electrical Overstress/Electrostatic Discharge (Anaheim, United States, 08/09/2005–16/09/2005)

2005

Résumé

This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.

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Titre: Physics and Design Optimization of ESD Diode for 0.13mm PD-SOI Technology
Créateurs - sans rôle: Christophe Entringer - STMicroelectronics [Crolles]
Philippe Flatresse - STMicroelectronics [Crolles]
Pascal Salomé - STMicroelectronics [Crolles]
Pascal Nouet - Conception et Test de Systèmes MICroélectroniques
Florence Azaïs - Conception et Test de Systèmes MICroélectroniques
Détails de publication: Electrical Overstress/Electrostatic Discharge Symposium
Colloque: EOS/ESD: Electrical Overstress/Electrostatic Discharge (Anaheim, United States, 08/09/2005–16/09/2005)
Identifiants: 9946058909311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00106041