Physical Extension of the Logical Effort Model

Benoit Lasbouygues; Robin M. Wilson; Philippe Maurine; Nadine Azemard; Daniel Auvergne

doi:10.1007/978-3-540-30205-6_86

Retour

Physical Extension of the Logical Effort Model

Acte de colloque

Open Access

Physical Extension of the Logical Effort Model

Benoit Lasbouygues, Robin M. Wilson, Philippe Maurine, Nadine Azemard et Daniel Auvergne

14th International Workshop on Power and Timing Modeling Optimization and Simulation, Vol.LNCS(3254), pp.838-848

PATMOS: Power And Timing Modeling, Optimization and Simulation (Santorini, Greece, 15/09/2004–17/09/2004)

2004

DOI: https://doi.org/10.1007/978-3-540-30205-6_86

Résumé

The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the library and appears to be sub-optimal for a complex implementation. This is due to the inability of this model in capturing I/O coupling and input ramp effects. In this paper, we introduce a physically based extension of the logical effort model, considering I/O coupling capacitance and input ramp effects. This extension of the logical effort model is deduced from an analysis of the supply gate switching process. Validation of this model is performed on 0.18µm and 0.13µm STM technologies. Application is given to the definition of a compact representation of CMOS library timing performance.

Fichiers et liens (1)

url

Find in HALAfficher

Indicateurs

1 Consultations de la notice

Détails

Titre: Physical Extension of the Logical Effort Model
Créateurs - sans rôle: Benoit Lasbouygues - STMicroelectronics (France)
Robin M. Wilson - STMicroelectronics (France)
Philippe Maurine - Université de Montpellier
Nadine Azemard - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Daniel Auvergne - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Détails de publication: 14th International Workshop on Power and Timing Modeling Optimization and Simulation, Vol.LNCS(3254), pp.838-848
Colloque: PATMOS: Power And Timing Modeling, Optimization and Simulation (Santorini, Greece, 15/09/2004–17/09/2004)
Identifiants: 9947371109311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00108895