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Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects
Acte de colloque   Open Access

Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects

João Azevedo, Arnaud Virazel, Yuanqing Cheng, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et Jérémy Alvarez-Hérault
5th International Conference on Advances in System Testing and Validation Lifecycle, pp.39-44
VALID: Advances in System Testing and Validation Lifecycle (Venice, Italy, 27/10/2013–01/11/2013)
2013

Résumé

Non-volatile memories Spintronics TAS-MRAM Capacitive defects Fault modeling Test

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