Résumé
Based on an incremental path search algorithm, this paper addresses the problem of longest combinational paths selection for performance optimization at physical level. A realistic evaluation of gate delay and controlled sizing techniques are used to manage the circuit path sizing alternatives, such as delay or power/area constraints. The efficiency of this technique is demonstrated and also illustrated on several ISCAS'85 benchmark circuits. A comparison is given between regular sizing alternatives to local optimization steps controlled by specific indicators.