P.SIZE: A Sizing aid for Optimized Designs

Nadine Azemard; Vincent Bonzom; Daniel Auvergne

doi:10.1109/EURDAC.1992.246248

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P.SIZE: A Sizing aid for Optimized Designs

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P.SIZE: A Sizing aid for Optimized Designs

Nadine Azemard, Vincent Bonzom et Daniel Auvergne

Proceedings EURO-DAC '92: European Design Automation Conference, pp.160-166

EURODAC 1992 - European Design Automation Conference (Hamburg, Germany, 07/09/1992–10/09/1992)

1992

DOI: https://doi.org/10.1109/EURDAC.1992.246248

Résumé

Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given.

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Détails

Titre: P.SIZE: A Sizing aid for Optimized Designs
Créateurs - sans rôle: Nadine Azemard - Université de Montpellier
Vincent Bonzom - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Daniel Auvergne - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Détails de publication: Proceedings EURO-DAC '92: European Design Automation Conference, pp.160-166
Colloque: EURODAC 1992 - European Design Automation Conference (Hamburg, Germany, 07/09/1992–10/09/1992)
Identifiants: 9945404809311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00239396