POPS: A tool for Delay/Power Performance/Optimization

Nadine Azemard; Michel Aline; Daniel Auvergne

doi:10.1109/ASIC.2000.880715

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POPS: A tool for Delay/Power Performance/Optimization

Nadine Azemard, Michel Aline et Daniel Auvergne

13th International ASIC/SOC Conference, pp.276-280

ASIC-SoC: International ASIC/SOC Conference (Arlington, VA, United States, 13/09/2000–16/09/2000)

2000

DOI: https://doi.org/10.1109/ASIC.2000.880715

Résumé

Based on an incremental path search algorithm, this paper addresses the problem of performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from industrial tools on examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.

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Détails

Titre: POPS: A tool for Delay/Power Performance/Optimization
Créateurs - sans rôle: Nadine Azemard - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Michel Aline - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Daniel Auvergne - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Détails de publication: 13th International ASIC/SOC Conference, pp.276-280
Colloque: ASIC-SoC: International ASIC/SOC Conference (Arlington, VA, United States, 13/09/2000–16/09/2000)
Identifiants: 9944642409311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00239434